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PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) FEATURES * * * * * * * * 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz - 800MHz (selectable 1x, 2x, 4x and 8x multipliers). Low Injection Power for crystal 50uW. Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Integrated variable capacitors. Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil. DIE CONFIGURATION OUTSEL0^ 65 mil OUTSEL1^ SEL0^ SEL1^ VDD VDD VDD VDD (1550,1475) 17 16 25 24 23 22 21 20 19 18 GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^ XIN XOUT SEL3^ 62 mil 26 27 Die ID: A1313-13A 15 28 14 13 SEL2^ OE CTRL VCON 29 12 DESCRIPTION PLL520-10 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with an integrated Phase Locked Loop for selectable 1x (no PLL), 2x, 4x or 8x multipliers. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. 11 30 C502A 31 1 2 3 4 5 6 7 8 10 9 Y (0,0) X DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil BLOCK DIAGRAM SEL OE VCON Oscillator Amplifier w/ X+ integrated varicaps XPLL (Phase Locked Loop) OUTPUT SELECTION AND ENABLE OUTSEL1 (Pad #18) 0 0 1 1 OUTSEL0 (Pad #25) 0 1 0 1 OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 Tri-state Output enabled Output enabled Tri-state Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Q Q PLL by-pass PLL520-10 OE_SELECT (Pad #9) 0 1 (Default) Pad #9: Bond to GND to set to "0", bond to VDD to set to "1" Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is "1" Logical states defined by CMOS levels if OE_SELECT is "0" 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 GNDBUF GND GND GND GND GND NC GND PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) FREQUENCY SELECTION TABLE Pad #28 SEL3 Pad #29 SEL2 Pad #19 SEL1 Pad #20 SEL0 Selected Multiplier 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 Fin x 8 Fin x 4 Fin x 2 No multiplication (no PLL) All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency SYMBOL CX+ CXC0 OF CONDITIONS 65MHz to 130 MHz (VDD=3.3V) MIN. TYP. MAX. 2 2 UNITS pF MHz 2.6 65 350 130 Fund. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW SYMBOL TVCXOSTB CONDITIONS From power valid FXIN = 100 - 200MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V VCON = 0 to 3.3V MIN. TYP. MAX. 10 UNITS ms ppm ppm pF % ppm/V k kHz 200* 100* 4 - 18* 10* 65 60 0V VCON 3.3V, -3dB 25 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL IDD VDD @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD - 1.3V (PECL) CONDITIONS PECL/LVDS/CMOS 2.97 45 45 45 50 50 50 50 MIN. TYP. MAX. 100/80/40 3.63 55 55 55 UNITS mA V % mA 5. Jitter Specifications PARAMETERS Period jitter RMS CONDITIONS 77.76MHz 155.52MHz 622.08MHz 77.76MHz 155.52MHz 622.08MHz Integrated 12 kHz to 20 MHz at 77.76MHz Integrated 12 kHz to 20 MHz at 155.52MHz Integrated 12 kHz to 20 MHz at 622.08MHz MIN. TYP. 2.5 4 5 24 29 32 0.5 1.5 1.5 MAX. UNITS ps Period jitter peak-to-peak ps Integrated jitter RMS ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 77.76MHz 155.52MHz 622.08MHz @10Hz -75 -75 -75 @100Hz -95 -95 -95 @1kHz -125 -120 -115 @10kHz -145 -125 -118 @100kHz -155 -123 -115 UNITS dBc/Hz Note: Phase Noise at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 7. CMOS Output Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL IOH IOL IOH IOL CONDITIONS VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V 0.3V ~ 3.0V with 15 pF load 0.3V ~ 3.0V with 15 pF load MIN. 30 30 10 10 TYP. MAX. UNITS mA mA mA mA 2.4 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 8. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL VOD VOD VOH VOL VOS VOS IOXD IOSD CONDITIONS MIN. 247 -50 TYP. 355 1.4 1.1 1.2 3 1 -5.7 MAX. 454 50 1.6 1.375 25 10 -8 UNITS mV mV V V V mV uA mA RL = 100 (see figure) 0.9 1.125 0 Vout = VDD or GND VDD = 0V 9. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS RL = 100 CL = 10 pF (see figure) MIN. 0.2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50 CL = 10pF VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 10. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL VOH VOL CONDITIONS RL = 50 to (VDD - 2V) (see figure) MIN. VDD - 1.025 MAX. VDD - 1.620 UNITS V V 11. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL tr tf CONDITIONS @20/80% - PECL @80/20% - PECL MIN. TYP. 0.6 0.5 MAX. 1.5 1.5 UNITS ns ns PECL Levels Test Circuit OUT VDD OUT PECL Output Skew 50 2.0V 50% 50 OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PAD ASSIGNMENT Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name GND GND GND GND GND N/C GND GNDBUF OE_SELECT LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 SEL1 SEL0 VDD VDD VDD VDD OUTSEL0 XIN XOUT SEL3 SEL2 OE_CTRL VCON X (m) 248 361 473 587 702 874 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1042 854 659 559 459 358 194 109 109 109 109 109 109 Y (m) 109 109 109 109 109 109 109 109 125 259 476 616 716 871 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 858 646 397 181 Ground. Ground. Ground. Ground. Ground. No Connection. Ground. Ground, Buffer circuitry. Used to select between PECL or CMOS logic states for OE. Internal pull up. LVDS output. PECL output. 3.3V power supply, Buffer circuitry. 3.3V power supply, Buffer circuitry. Complementary PECL output. Complementary LVDS output. CMOS output Ground, Buffer Circuitry. Used to select CMOS, PECL or LVDS output type. Internal pull up. Used to select multiplication factor. Internal pull up. Used to select multiplication factor. Internal pull up. 3.3V power supply. 3.3V power supply. 3.3V power supply. 3.3V power supply. Used to select CMOS, PECL or LVDS output type. Internal pull up. Crystal input. See crystal specification page 2. Crystal output. See crystal specification page 2. Used to select multiplication factor. Internal pull up. Used to select multiplication factor. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Voltage control input. Description 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-10 D C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D=DIE Order Number PLL520-10DC Marking P520-10DC Package Option Die - Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 8 |
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